The invention relates to electrical testing of an IC component and, in particular, to a test structure of a device monitor.
Integrated circuits are typically fabricated on a semiconductor wafer. After semiconductor processing is finished, the wafer is sawed into multiple chips. Before die sawing, the chips are arranged in an array on the wafer and divided by scribe lines or streets. To enhance utilization of wafer area, these scribe lines or streets receive device monitors. Devices under test are embedded in the device monitors. The structures of the devices under test are the same as components in the wafer and are fabricated with the same process. Thus, by measuring the devices under test operating under different conditions, it is known whether the components comply with the model on which the chip design is based. Behavior of the chip can be predicted before die sawing or chip testing with expensive testers so that production cost can be reduced. Accordingly, to obtain accurate measurement results with minimum chip area occupied by the device monitors becomes important.
Conventional device monitors are categorized according to operating frequency. One group is suitable for measurement under DC or very low frequency (˜1 MHz). The other group is suitable for measurement under very high frequency. The device monitors for very high frequency are also divided into two groups as follows.
The first group of device monitors is a GS (ground-signal) type test structure, as shown in FIG. 1, disclosed in U.S. Pat. No. 5,942,766. The test structure is located at the intersection of two scribe lines such that part of the test structure is in the first scribe line while other part is in the second scribe line. Thus, the test structure accommodates a narrower scribe line (˜100 um).
The second group of device monitors is GSG (ground-signal-ground) type test structure, as shown in FIGS. 2 and 3. Symmetry of the GSG test structures guarantees symmetry of the electromagnetic field. Better EM field termination from a signal end to a ground end is also provided so that interference can be minimized. Thus, measurement accuracy in high frequency environment can be improved. The GSG type test structure disclosed in U.S. Pat. No. 6,194,739 is shown in FIG. 3. Six pads thereof are arranged substantially in line with a device under test (DUT) so that the test structure accommodates a narrower scribe line. The DUT mentioned herein is typically a metal oxide semiconductor field effect transistor (MOSFET) or a bipolar junction transistor (BJT).
In addition, in traditional RF test structures in FIGS. 2 and 3, to obtain accurate high frequency measurement results of four terminal DUTS, such as a MOSFET or a BJT, two ends other than the input and output are connected. Accordingly, the test structures cannot be used for DC electrical parameter extraction when the two ends require a specific bias condition for each terminal.